The integration of carbon nanostructures as channel materials in the next generation of electronic devices offers many advantages over the continued scaling of silicon (Si). Carbon nanostructures such as carbon nanotubes and graphene are two nanoscale forms of carbon that exhibit extremely high current carrying capacity and mobilities, which are several orders of magnitude beyond the theoretical limit for Si. Furthermore, carbon nanotubes (one-dimensional) and graphene (two-dimensional) are low-dimensional (ultra-thin-body) materials, which allows them to be aggressively scaled in FETs (field-effect transistors) without incurring deleterious short-channel effects that hinder modern scaled devices.
With some conventional FET structures having channels formed of carbon nanotube or graphene, there is overlap between the source/drain electrodes and the gate electrode such that the channel region between the source/drain electrodes is completely gated. However, the overlap between the source/drain electrodes and the gate electrode results in parasitic capacitance, which degrades the circuit performance. To reduce this parasitic capacitance, some conventional FET structures having carbon nanotube or graphene channels are formed having non-overlapping source/drain and gate electrodes With these structures, a performance bottleneck arises due to a high parasitic resistance in the un-gated portion of the channel that results from the underlap between the source/drain electrodes and the gate.
In particular, with conventional FET structures, spacers are used to isolate the gate electrode form the source and drain electrodes. The un-gated channel region under the spacer provides a high resistance region within the channel of the FET. With conventional Si CMOS devices, extension doping can be used to reduce the resistance of the channel region under the spacers. However, with graphene and carbon nanotube FET devices, the channel cannot be doped by conventional methods. Thus, methods for reducing the parasitic resistance of un-gated regions of carbon nanostructure channels of FETs are desired.